1. Technical Field
This subject matter disclosed herein is generally directed to the field of packaging of integrated circuit devices, and, more particularly, to a packed flip chip with an interposer, and various methods of making same.
2. Description of the Related Art
Integrated circuit technology uses electrical devices, e.g., transistors, resistors, capacitors, etc., to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever-increasing number of linked electrical devices so that the circuit may perform its intended function. As the number of transistors increases, the integrated circuitry dimensions shrink. One challenge in the semiconductor industry is to develop improved methods for electrically connecting and packaging circuit devices which are fabricated on the same and/or on different wafers or chips. In general, it is desirable in the semiconductor industry to construct transistors which occupy less surface area on the silicon chip/die.
In the manufacture of semiconductor device assemblies, a single semiconductor die is most commonly incorporated into each sealed package. Many different package styles are used, including dual inline packages (DIP), zig-zag inline packages (ZIP), small outline J-bends (SOJ), thin small outline packages (TSOP), plastic leaded chip carriers (PLCC), small outline integrated circuits (SOIC), plastic quad flat packs (PQFP) and interdigitated leadframe (IDF). Some semiconductor device assemblies are connected to a substrate, such as a circuit board, prior to encapsulation. Manufacturers are under constant pressure to reduce the size of the packaged integrated circuit device and to increase the packaging density in packaging integrated circuit devices.
There are many applications where a plurality of integrated circuit die are attached to a single module that is commonly referred to as a multi-chip module. In some cases, traditional flip chip techniques have been employed to electrically couple an integrated circuit die to the module. In some cases, after the die is attached to the module, an underfill material is positioned between the integrated circuit die and the module in an effort to enhance the stability of the conductive connection between the integrated circuit die and the multi-chip module. The underfill material is typically applied by dispensing a quantity of the underfill material and allowing it to wick under the integrated circuit die and fill the space between the die and the multi-chip module. Thereafter, the underfill material is cured. The use of such underfill material can be time-consuming and expensive, especially if it is required on large surface areas.
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.